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Browsing by Subject "Computer architecture"
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Item Auto-Generating Models From Their Semantics and Constraints(2013-08-20) Pati, Tanumoy; Hill, James H. (James Haswell); Raje, Rajeev; Al Hasan, MohammadDomain-specific models powered using domain-specific modeling languages are traditionally created manually by modelers. There exist model intelligence techniques, such as constraint solvers and model guidance, which alleviate challenges associated with manually creating models, however parts of the modeling process are still manual. Moreover, state-of-the-art model intelligence techniques are---in essence---reactive (i.e., invoked by the modeler). This thesis therefore provides two contributions to model-driven engineering research using domain-specific modeling language (DSML). First, it discusses how DSML semantic and constraint can enable proactive modeling, which is a form of model intelligence that foresees model transformations, automatically executes these model transformations, and prompts the modeler for assistance when necessary. Secondly, this thesis shows how we integrated proactive modeling into the Generic Modeling environment (GME). Our experience using proactive modeling shows that it can reduce modeling effort by both automatically generating required model elements, and by guiding modelers to select what actions should be executed on the model.Item Deployment of Compressed MobileNet V3 on iMX RT 1060(IEEE Xplore, 2021-04) Prasad, S. P. Kavyashree; El-Sharkawy, Mohamed; Electrical and Computer Engineering, School of Engineering and TechnologyDeep Neural Networks (DNN) are prominent in most applications today. From self-driving cars, sentiment analysis, surveillance systems, and robotics, they have been used extensively. Among DNNs, Convolutional Neural Networks (CNN) have achieved massive success in computer vision applications as the human visual system inspires their architecture. However, striving to achieve higher accuracies, CNN complexity, parameters, and layers were increased, which led to a drastic surge in their size, making their deployment challenging. Over the years, many researchers have proposed various techniques to alleviate this issue-one of them being Design Space Exploration (DSE) to minimize size and computation with little compromise to accuracy. MobileNet V3 is one such architecture designed to achieve good accuracy while being mindful of resources. It produces an accuracy of 88.93% on CIFAR-10 with a size of 15.3MB. This paper further reduces its size to 2.3MB while boosting its accuracy to 89.13% using DSE techniques. It is then deployed into NXP's i.MX RT1060 Advanced Driver Assistance System (ADAS) platform.Item A Dynamically Configurable Discrete Event Simulation Framework for Many-Core System-on-Chips(2010) Barnes, Christopher J.; Lee, Jaehwan John; King, Brian S.; Chien, Yung Ping StanleyIndustry trends indicate that many-core heterogeneous processors will be the next-generation answer to Moore's law and reduced power consumption. Thus, both academia and industry are focused on the challenges presented by many-core heterogeneous processor designs. In many cases, researchers use discrete event simulators to research and validate new computer architecture innovations. However, there is a lack of dynamically configurable discrete event simulation environments for the testing and development of many-core heterogeneous processors. To fulfill this need we present Mhetero, a retargetable framework for cycle-accurate simulation of heterogeneous many-core processors along with the cycle-accurate simulation of their associated network-on-chip communication infrastructure. Mhetero is the result of research into dynamically configurable and highly flexible simulation tools with which users are free to produce custom instruction sets and communication methods in a highly modular design environment. In this thesis we will discuss our approach to dynamically configurable discrete event simulation and present several experiments performed using the framework to exemplify how Mhetero, and similarly constructed simulators, may be used for future innovations.Item HBONext: HBONet with Flipped Inverted Residual(IEEE Xplore, 2021-06) Joshi, Sanket Ramesh; El-Sharkawy, Mohamed; Electrical and Computer Engineering, School of Engineering and TechnologyThe top-performing deep CNN (DCNN) architectures are presented every year based on their compatibility and performance ability on the embedded edge applications, significantly for image classification. There are many obstacles in making these neural network architectures hardware friendly due to the limited memory, lesser computational resources, and the energy requirements of these devices. The addition of Bottleneck modules has further helped this classification problem, which explores the channel interdependencies, using either depthwise or groupwise convolutional features. The classical inverted residual block, a well-known design methodology, has now gained more attention due to its growing popularity in portable applications. This paper presents a mutated version of Harmonious Bottlenecks (DHbneck) with a Flipped version of Inverted Residual (FIR), which outperforms the existing HBONet architecture by giving the best accuracy value and the miniaturized model size. This FIR block performs identity mapping and spatial transformation at its higher dimensions, unlike the existing concept of inverted residual. The devised architecture is tested and validated using CIFAR-10 public dataset. The baseline HBONet architecture has an accuracy of 80.97% when tested on CIFAR-10 dataset and the model's size is 22 MB. In contrast, the proposed architecture HBONext has an improved validation accuracy of 88.30% with a model reduction to a size of 7.66 MB.