Electrical & Computer Engineering Department Theses and Dissertations

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Emission control in rotary kiln limestone calcination using Petri net models
(2016-08) Saini, Amit K.; Li, Lingxi; King, Brian; Agarwal, Mangilal
The idea of emission control is not new. Different industries have been putting in a lot of effort to limit the harmful emissions and support the environment. Keeping our earth green and safe for upcoming generations is our responsibility. Many cement plants have been shut down in recent years on account of high emissions. Controlling SO2, NOx and CO emissions using the Petri net models is an effort towards the clean production of cement. Petri nets do not just give a pictorial representation of emission control, but also help in designing a controller. A controlled Petri net can be potentially implemented to control the process parameters. In Chapter 2, we discuss the Petri nets in detail. In Chapter 3, we explain the modeling of emissions using the Petri nets. A controlled emission model is given in Chapter 4. A general Petri net model is considered to design the controller, which can be easily modified depending on the specific requirements and type of kiln in consideration. The future work given at the end is the work in progress and a neural network model will likely be integrated with the Petri net model.
Fabrication and analysis of CIGS nanoparticle-based thin film solar cells
(2013-11-20) Ghane, Parvin; Varahramyan, Kody; Agarwal, Mangilal; Rizkalla, Maher E.; King, Brian
Fabrication and analysis of Copper Indium Gallium di-Selenide (CIGS) nanoparticles-based thin film solar cells are presented and discussed. This work explores non-traditional fabrication processes, such as spray-coating for the low-cost and highly-scalable production of CIGS-based solar cells. CIGS nanoparticles were synthesized and analyzed, thin CIGS films were spray-deposited using nanoparticle inks, and resulting films were used in low-cost fabrication of a set of CIGS solar cell devices. This synthesis method utilizes a chemical colloidal process resulting in the formation of nanoparticles with tunable band gap and size. Based on theoretical and experimental studies, 100 nm nanoparticles with an associated band gap of 1.33 eV were selected to achieve the desired film characteristics and device performances. Scanning electron microcopy (SEM) and size measurement instruments (Zetasizer) were used to study the size and shape of the nanoparticles. Electron dispersive spectroscopy (EDS) results confirmed the presence of the four elements, Copper (Cu), Indium (In), Gallium (Ga), and Selenium (Se) in the synthesized nanoparticles, while X-ray diffraction (XRD) results confirmed the tetragonal chalcopyrite crystal structure. The ultraviolet-visible-near infra-red (UV-Vis-NIR) spectrophotometry results of the nanoparticles depicted light absorbance characteristics with good overlap against the solar irradiance spectrum. The depositions of the nanoparticles were performed using spray-coating techniques. Nanoparticle ink dispersed in ethanol was sprayed using a simple airbrush tool. The thicknesses of the deposited films were controlled through variations in the deposition steps, substrate to spray-nozzle distance, size of the nozzle, and air pressure. Surface features and topology of the spray-deposited films were analyzed using atomic force microscopy (AFM). The deposited films were observed to be relatively uniform with a minimum thickness of 400 nm. Post-annealing of the films at various temperatures was studied for the photoelectric performance of the deposited films. Current density and voltage (J/V) characteristics were measured under light illumination after annealing at different temperatures. It was observed that the highest photoelectric effect resulted in annealing temperatures of 150-250 degree centigrade under air atmosphere. The developed CIGS films were implemented in solar cell devices that included Cadmium Sulfide (CdS) and Zinc Oxide (ZnO) layers. The CdS film served as the n-type layer to form a pn junction with the p-type CIGS layer. In a typical device, a 300 nm CdS layer was deposited through chemical bath deposition on a 1 $mu$m thick CIGS film. A thin layer of intrinsic ZnO was spray coated on the CdS film to prevent shorting with the top conductor layer, 1.5 μm spray-deposited aluminum doped ZnO layer. A set of fabricated devices were tested using a Keithley semiconductor characterization instrument and micromanipulator probe station. The highest measured device efficiency was 1.49%. The considered solar cell devices were simulated in ADEPT 2.0 solar cell simulator based on the given fabrication and experimental parameters. The simulation module developed was successfully calibrated with the experimental results. This module can be used for future development of the given work.
Influence of Size and Interface Effects of Silicon Nanowire and Nanosheet for Ultra-Scaled Next Generation Transistors
(2020-08) Sikder, Orthi; Schubert, Peter J; Rizkalla, Maher E.; Agarwal, Mangilal
In this work, we investigate the trade-off between scalability and reliability for next generation logic-transistors i.e. Gate-All-Around (GAA)-FET, Multi-Bridge-Channel (MBC)-FET. First, we analyze the electronic properties (i.e. bandgap and quantum conductance) of ultra-thin silicon (Si) channel i.e. nano-wire and nano-sheet based on first principle simulation. In addition, we study the influence of interface states (or dangling bonds) at Si-SiO2 interface. Second, we investigate the impact of bandgap change and interface states on GAA-FETs and MBC-FETs characteristics by employing Non-equilibrium Green's Function based device simulation. In addition to that we calculate the activation energy of Si-H bond dissociation at Si-SiO2 interface for different Si nano-wire/sheet thickness and different oxide electric- field. Utilizing these thickness dependent activation energies for corresponding oxide electric- field, in conjunction with reaction-diffusion model, we compute the characteristics shift and analyze the negative bias temperature instability in GAA-FET and MBC-FET. Based on our analysis, we estimate the operational voltage of these transistors for a life-time of 10 years and the ON current of the device at iso-OFF-current condition. For example, for channel length of 5 nm and thickness < 5 nm the safe operating voltage needs to be < 0.55V. Furthermore, our analysis suggests that the benefi t of Si thickness scaling can potentially be suppressed for obtaining a desired life-time of GAA-FET and MBC-FET.
Low-power ASIC design with integrated multiple sensor system
(2013-08) Jafarian, Hossein; Varahramyan, Kody; Rizkalla, Maher E.; Agarwal, Mangilal; Shrestha, Sudhir; King, Brian
A novel method of power management and sequential monitoring of several sensors is proposed in this work. Application specific integrated circuits (ASICs) consisting of analog and digital sub-systems forming a system on chip (SoC) has been designed using complementary metal-oxide-semiconductor (CMOS) technology. The analog sub-system comprises the sensor-drivers that convert the input voltage variations to output pulse-frequency. The digital sub-system includes the system management unit (SMU), counter, and shift register modules. This performs the power-usagemanagement, sensor-sequence-control, and output-data-frame-generation functions. The SMU is the key unit within the digital sub-system is that enables or disables a sensor. It captures the pulse waves from a sensor for 3 clocks out of a 16-clock cycle, and transmits the signal to the counter modules. As a result, the analog sub-system is at on-state for only 3/16th fraction (18 %) of the time, leading to reduced power consumption. Three cycles is an optimal number selected for the presented design as the system is unstable with less than 3 cycles and higher clock cycles results in increased power consumption. However, the system can achieve both higher sensitivity and better stability with increased on-state clock cycles. A current-starved-ring-oscillator generates pulse waves that depend on the sensor input parameter. By counting the number of pulses of a sensor-driver in one clock cycle, a sensor input parameter is converted to digital. The digital sub-system constructs a 16-bit frame consisting of 8-bit sensor data, start and stop bits, and a parity bit. Ring oscillators that drive capacitance and resistance-based sensors use an arrangement of delay elements with two levels of control voltages. A bias unit which provides these two levels of control voltages consists of CMOS cascade current mirror to maximize voltage swing for control voltage level swings which give the oscillator wider tuning range and lower temperature induced variations. The ring oscillator was simulated separately for 250 nm and 180 nm CMOS technologies. The simulation results show that when the input voltage of the oscillator is changed by 1 V, the output frequency changes linearly by 440 MHz for 180 nm technology and 206 MHz for 250 nm technology. In a separate design, a temperature sensitive ring oscillator with symmetrical load and temperature dependent input voltage was implemented. When the temperature in the simulation model was varied from -50C to 100C the oscillator output frequency reduced by 510 MHz for the 250 nm and by 810 MHz for 180 nm CMOS technologies, respectively. The presented system does not include memory unit, thus, the captured sensor data has to be instantaneously transmitted to a remote station, e.g. end user interface. This may result in a loss of sensor data in an event of loss of communication link with the remote station. In addition, the presented design does not include transmitter and receiver modules, and thus necessitates the use of separate modules for the transfer of the data.
Paper-based lithium-Ion batteries using carbon nanotube-coated wood microfiber current collectors
(2013-11-06) Aliahmad, Nojan; Varahramyan, Kody; Agarwal, Mangilal; Shrestha, Sudhir; Rizkalla, Maher E.; King, Brian
The prevalent applications of energy storage devices have incited wide-spread efforts on production of thin, flexible, and light-weight lithium-ion batteries. In this work, lithium-ion batteries using novel flexible paper-based current collectors have been developed. The paper-based current collectors were fabricated from carbon nanotube (CNT)-coated wood microfibers (CNT-microfiber paper). This thesis presents the fabrication of the CNT-microfiber paper using wood microfibers, coating electrode materials, design and assemblies of battery, testing methodologies, and experimental results and analyses. Wood microfibers were coated with carbon nanotubes and poly(3,4-ethylenedioxythiophene) (PEDOT) through an electrostatic layer-by-layer nanoassembely process and formed into a sheet, CNT-microfiber paper. The CNT loading of the fabricated paper was measured 10.1 μg/cm2 subsequently considered. Electrode material solutions were spray-coated on the CNT-microfiber paper to produce electrodes for the half and full-cell devices. The CNT current collector consists of a network structure of cellulose microfibers at the micro-scale, with micro-pores filled with the applied conductive electrode materials reducing the overall internal resistance for the cell. A bending test revealed that the paper-based electrodes, compared to metal ones, incurred fewer damages after 20 bends at an angle of 300o. The surface fractures on the paper-based electrodes were shallow and contained than metallic-based electrodes. The micro-pores in CNT-microfiber paper structure provides better adherence to the active material layer to the substrate and inhibits detachment while bending. Half-cells and full-cells using lithium cobalt oxide (LCO), lithium titanium oxide (LTO), and lithium magnesium oxide (LMO) were fabricated and tested. Coin cell assembly and liquid electrolyte was used. The capacities of half-cells were measured 150 mAh/g with LCO, 158 mAh/g with LTO, and 130 mAh/g with LMO. The capacity of the LTO/LCO full-cell also was measured 126 mAh/g at C/5 rate. The columbic efficiency of the LTO/LCO full-cell was measured 84% for the first charging cycle that increased to 96% after second cycle. The self-discharge test of the full-cell after charging to 2.7 V at C/5 current rate is showed a stable 2 V after 90 hours. The capacities of the developed batteries at lower currents are comparable to the metallic electrode-based devices, however, the capacities were observed to drop at higher currents. This makes the developed paper-based batteries more suitable for low current applications, such as, RFID tags, flexible electronics, bioassays, and displays. The capacities of the batteries at higher current can be improved by enhancing the conductivity of the fibers, which is identified as the future work. Furthermore, fabrication of an all solid state battery using solid electrolyte is also identified as the future work of this project.
Silicon Based Nano-electronic Synaptic Device for Neuromorphic Hardware
(2024-08) Sikder, Orthi; Schubert, Peter; King, Brian; Rizkalla, Maher; Agarwal, Mangilal
Porous silicon (po-Si) is a unique form of silicon (Si) that features tunable nanopores distributed throughout its bulk structure. While crystalline Si (c-Si) already boasts technological advantages, po-Si offers an additional key aspect with its large surface area relative to its small volume, making it highly conducive to surface chemistry. In this research, our focus centers on the design of a synaptic device based on po-Si, exploring its potential for neuromorphic hardware applications. To begin, we delve into the analysis of several electrical properties of po-Si using density functional theory (ab initio/first principles) calculations. Notably, we discover the presence of intra-pore dangling states within the bandgap region of po-Si. Although po-Si is known for its higher bandgap compared to c-Si, resulting in low carrier density and increased resistance, the existence of these dangling states significantly impacts its electronic transport. Additionally, we investigate the electric field driven modulation of dangling bonds through controlled intra-pore Si-H bond dissociation. This modulation enables precise control over the density of dangling states, facilitating the tunability of po-Si conductance. Theoretically evaluating the current-voltage characteristics of our proposed po-Si based synaptic devices, we determine the potential range of obtainable conductivity. Finally, we evaluate the performance by integrating porous silicon nanoelectronics devices into neural networks. These devices exhibit superior synaptic plasticity, faster response times, and reduced power consumption compared to other synapses. The research indicates that porous-silicon devices are highly effective in neuromorphic systems, paving the way for more efficient and scalable neural networks. These advancements have significant practical and cost-effective implications for a wide range of applications, including pattern recognition, machine learning, and artificial intelligence. Overall, our analyses reveal that the integration of po-Si based synaptic devices into the neural fabric offers a path towards achieving significantly denser and more energy-efficient neuromorphic hardware. With its tunable properties, large surface area, and potential for controlled conductance, po-Si emerges as a promising candidate for the development of advanced silicon-based nano-electronic devices tailored for neuromorphic computing. As we delve deeper into the potentials of po-Si, the era of cognitive computing, inspired by the elegance of bio-mimetic neural networks, edges closer to becoming a reality.
Smart shoe gait analysis and diagnosis: designing and prototyping of hardware and software
(2018) Peddinti, Seshasai Vamsi Krishna; Agarwal, Mangilal; Rizkalla, Maher; El-Sharkawy, Mohamed‏
Gait analysis plays a major role in treatment of osteoarthritis, knee or hip replacements, and musculoskeletal diseases. It is extensively used for injury rehabilitation and physical therapy for issues like Hemiplegia and Diplegia. It also provides us with the information to detect various improper gaits such as Parkinson's disease, Hemiplegic and diplegic gaits. Though there are many wearable and non-wearable methods to detect the improper gate performance, they are usually not user friendly and have restrictions. Most existing devices and systems can detect the gait but are very limited with regards of diagnosing them. The proposed method uses two A201 Force sensing resistors, accelerometer, and gyroscope to detect the gait and send diagnosed information of the possibility of the specified improper gaits via Bluetooth wireless communication system to the user's hand-held device or the desktop. The data received from the sensors was analyzed by the custom made micro-controller and is sent to the desktop or mobile device via Bluetooth module. The peak pressure values during a gait cycle were recorded and were used to indicate if the walk cycle of a person is normal or it has any abnormality. Future work: A magnetometer can be added to get more accurate results. More improper gaits can be detected by using two PCBs, one under each foot. Data can be sent to cloud and saved for future comparisons.

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Browsing Electrical & Computer Engineering Department Theses and Dissertations by Author "Agarwal, Mangilal"

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