Parallel acceleration of deadlock detection and avoidance algorithms on GPUs

dc.contributor.advisorLee, Jaehwan John
dc.contributor.authorAbell, Stephen W.
dc.contributor.otherKing, Brian
dc.contributor.otherChien, Stanley
dc.date.accessioned2013-11-06T15:09:38Z
dc.date.available2014-11-07T10:30:22Z
dc.date.issued2013-08
dc.degree.date2013en_US
dc.degree.disciplineElectrical & Computer Engineeringen
dc.degree.grantorPurdue Universityen_US
dc.degree.levelM.S.E.C.E.en_US
dc.descriptionIndiana University-Purdue University Indianapolis (IUPUI)en_US
dc.description.abstractCurrent mainstream computing systems have become increasingly complex. Most of which have Central Processing Units (CPUs) that invoke multiple threads for their computing tasks. The growing issue with these systems is resource contention and with resource contention comes the risk of encountering a deadlock status in the system. Various software and hardware approaches exist that implement deadlock detection/avoidance techniques; however, they lack either the speed or problem size capability needed for real-time systems. The research conducted for this thesis aims to resolve issues present in past approaches by converging the two platforms (software and hardware) by means of the Graphics Processing Unit (GPU). Presented in this thesis are two GPU-based deadlock detection algorithms and one GPU-based deadlock avoidance algorithm. These GPU-based algorithms are: (i) GPU-OSDDA: A GPU-based Single Unit Resource Deadlock Detection Algorithm, (ii) GPU-LMDDA: A GPU-based Multi-Unit Resource Deadlock Detection Algorithm, and (iii) GPU-PBA: A GPU-based Deadlock Avoidance Algorithm. Both GPU-OSDDA and GPU-LMDDA utilize the Resource Allocation Graph (RAG) to represent resource allocation status in the system. However, the RAG is represented using integer-length bit-vectors. The advantages brought forth by this approach are plenty: (i) less memory required for algorithm matrices, (ii) 32 computations performed per instruction (in most cases), and (iii) allows our algorithms to handle large numbers of processes and resources. The deadlock detection algorithms also require minimal interaction with the CPU by implementing matrix storage and algorithm computations on the GPU, thus providing an interactive service type of behavior. As a result of this approach, both algorithms were able to achieve speedups over two orders of magnitude higher than their serial CPU implementations (3.17-317.42x for GPU-OSDDA and 37.17-812.50x for GPU-LMDDA). Lastly, GPU-PBA is the first parallel deadlock avoidance algorithm implemented on the GPU. While it does not achieve two orders of magnitude speedup over its CPU implementation, it does provide a platform for future deadlock avoidance research for the GPU.en_US
dc.identifier.urihttps://hdl.handle.net/1805/3653
dc.identifier.urihttp://dx.doi.org/10.7912/C2/2597
dc.language.isoen_USen_US
dc.subjectDeadlock Detectionen_US
dc.subjectResource Allocation Graph (RAG)en_US
dc.subjectGPUen_US
dc.subjectCUDAen_US
dc.subjectBit Vectoren_US
dc.subject.lcshGraphics processing units -- Programmingen_US
dc.subject.lcshImage processing -- Digital techniquesen_US
dc.subject.lcshElectronic data processing -- Distributed processingen_US
dc.subject.lcshComputer graphicsen_US
dc.subject.lcshOperating systems (Computers)en_US
dc.subject.lcshEngineering graphicsen_US
dc.subject.lcshComputer software -- Testingen_US
dc.subject.lcshVector analysisen_US
dc.subject.lcshReal-time programming -- Researchen_US
dc.subject.lcshComputer algorithms -- Researchen_US
dc.titleParallel acceleration of deadlock detection and avoidance algorithms on GPUsen_US
dc.typeThesisen
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