Browsing by Subject "Nanoelectronics"

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    Influence of Size and Interface Effects of Silicon Nanowire and Nanosheet for Ultra-Scaled Next Generation Transistors
    (2020-08) Sikder, Orthi; Schubert, Peter J; Rizkalla, Maher E.; Agarwal, Mangilal
    In this work, we investigate the trade-off between scalability and reliability for next generation logic-transistors i.e. Gate-All-Around (GAA)-FET, Multi-Bridge-Channel (MBC)-FET. First, we analyze the electronic properties (i.e. bandgap and quantum conductance) of ultra-thin silicon (Si) channel i.e. nano-wire and nano-sheet based on first principle simulation. In addition, we study the influence of interface states (or dangling bonds) at Si-SiO2 interface. Second, we investigate the impact of bandgap change and interface states on GAA-FETs and MBC-FETs characteristics by employing Non-equilibrium Green's Function based device simulation. In addition to that we calculate the activation energy of Si-H bond dissociation at Si-SiO2 interface for different Si nano-wire/sheet thickness and different oxide electric- field. Utilizing these thickness dependent activation energies for corresponding oxide electric- field, in conjunction with reaction-diffusion model, we compute the characteristics shift and analyze the negative bias temperature instability in GAA-FET and MBC-FET. Based on our analysis, we estimate the operational voltage of these transistors for a life-time of 10 years and the ON current of the device at iso-OFF-current condition. For example, for channel length of 5 nm and thickness < 5 nm the safe operating voltage needs to be < 0.55V. Furthermore, our analysis suggests that the benefi t of Si thickness scaling can potentially be suppressed for obtaining a desired life-time of GAA-FET and MBC-FET.
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    Molecular Dynamics Simulations of the Mechanical Deformation Behavior of Face-Centered Cubic Metallic Nanowires
    (2010-05-05T14:41:16Z) Heidenreich, Joseph David; Wang, Guofeng; Chen, Jie; Jones, Alan
    Nanoscale materials have become an active area of research due to the enhanced mechanical properties of the nanomaterials in comparison to their respective bulk materials. The effect that the size and shape of a nanomaterial has on its mechanical properties is important to understand if these materials are to be used in engineering applications. This thesis presents the results of molecular dynamics (MD) simulations on copper, gold, nickel, palladium, platinum, and silver nanowires of three cross-sectional shapes and four diameters. The cross-sectional shapes investigated were square, circular, and octagonal while the diameters varied from one to eight nanometers. Due to a high surface area to volume ratio, nanowires do not have the same atomic spacing as bulk materials. To account for this difference, prior to tensile loading, a minimization procedure was applied to find the equilibrium strain for each structure size and shape. Through visualization of the atomic energy before and after minimization, it was found that there are more than two energetically distinct areas within the nanowires. In addition, a correlation between the anisotropy of a material and its equilibrium strain was found. The wires were then subjected to a uniaxial tensile load in the [100] direction at a strain rate of 108 s-1 with a simulation temperature of 300 K. The embedded-atom method (EAM) was employed using the Foiles potential to simulate the stretching of the wires. The wires were stretched to failure, and the corresponding stress-strain curves were produced. From these curves, mechanical properties including the elastic modulus, yield stress and strain, and ultimate strain were calculated. In addition to the MD approach, an energy method was applied to calculate the elastic modulus of each nanowire through exponential fitting of an energy function. Both methods used to calculate Young’s modulus qualitatively gave similar results indicating that as diameter decreases, Young’s modulus decreases. The MD simulations were also visualized to investigate the deformation and yield behavior of each nanowire. Through the visualization, most nanowires were found to yield and fail through partial dislocation nucleation and propagation leading to {111} slip. However, the 5 nm diameter octagonal platinum nanowire was found to yield through reconstruction of the {011} surfaces into the more energetically favorable {021} surfaces.
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    Silicon Based Nano-electronic Synaptic Device for Neuromorphic Hardware
    (2024-08) Sikder, Orthi; Schubert, Peter; King, Brian; Rizkalla, Maher; Agarwal, Mangilal
    Porous silicon (po-Si) is a unique form of silicon (Si) that features tunable nanopores distributed throughout its bulk structure. While crystalline Si (c-Si) already boasts technological advantages, po-Si offers an additional key aspect with its large surface area relative to its small volume, making it highly conducive to surface chemistry. In this research, our focus centers on the design of a synaptic device based on po-Si, exploring its potential for neuromorphic hardware applications. To begin, we delve into the analysis of several electrical properties of po-Si using density functional theory (ab initio/first principles) calculations. Notably, we discover the presence of intra-pore dangling states within the bandgap region of po-Si. Although po-Si is known for its higher bandgap compared to c-Si, resulting in low carrier density and increased resistance, the existence of these dangling states significantly impacts its electronic transport. Additionally, we investigate the electric field driven modulation of dangling bonds through controlled intra-pore Si-H bond dissociation. This modulation enables precise control over the density of dangling states, facilitating the tunability of po-Si conductance. Theoretically evaluating the current-voltage characteristics of our proposed po-Si based synaptic devices, we determine the potential range of obtainable conductivity. Finally, we evaluate the performance by integrating porous silicon nanoelectronics devices into neural networks. These devices exhibit superior synaptic plasticity, faster response times, and reduced power consumption compared to other synapses. The research indicates that porous-silicon devices are highly effective in neuromorphic systems, paving the way for more efficient and scalable neural networks. These advancements have significant practical and cost-effective implications for a wide range of applications, including pattern recognition, machine learning, and artificial intelligence. Overall, our analyses reveal that the integration of po-Si based synaptic devices into the neural fabric offers a path towards achieving significantly denser and more energy-efficient neuromorphic hardware. With its tunable properties, large surface area, and potential for controlled conductance, po-Si emerges as a promising candidate for the development of advanced silicon-based nano-electronic devices tailored for neuromorphic computing. As we delve deeper into the potentials of po-Si, the era of cognitive computing, inspired by the elegance of bio-mimetic neural networks, edges closer to becoming a reality.