Browsing by Subject "GNRFET"

Now showing 1 - 2 of 2
  • Thumbnail Image
    Item
    High Performance GNRFET Devices for High-Speed Low-Power Analog and Digital Applications
    (2019-05) Patnala, Mounica; Rizkalla, Maher E.; King, Brian S.; Sharkawy, Mohamed El; Ytterdal, Trond
    Recent ULSI (ultra large scale integration) technology emphasizes small size devices, featuring low power and high switching speed. Moore's law has been followed successfully in scaling down the silicon device in order to enhance the level of integration with high performances until conventional devices failed to cop up with further scaling due to limitations with ballistic effects, and challenges with accommodating dopant fluctuation, mobility degradation, among other device parameters. Recently, Graphene based devices o ered alternative approach, featuring small size and high performances. This includes high carrier mobility, high carrier density, high robustness, and high thermal conductivity. These unique characteristics made the Graphene devices attractive for high speed electronic architectures. In this research, Graphene devices were integrated into applications with analog, digital, and mixed signals based systems. Graphene devices were briefly explored in electronics applications since its first model developed by the University of Illinois, Champaign in 2013. This study emphasizes the validation of the model in various applications with analog, digital, and mixed signals. At the analog level, the model was used for voltage and power amplifiers; classes A, B, and AB. At the digital level, the device model was validated within the universal gates, adders, multipliers, subtractors, multiplexers, demultiplexers, encoders, and comparators. The study was also extended to include Graphene devices for serializers, the digital systems incorporated into the data structure storage. At the mixed signal level, the device model was validated for the DACs/ADCs. In all components, the features of the new devices were emphasized as compared with the existing silicon technology. The system functionality and dynamic performances were also elaborated. The study also covered the linearity characteristics of the devices within full input range operation. GNRFETs with a minimum channel length of 10nm and an input voltage 0.7V were considered in the study. An electronic design platform ADS (Advanced Design Systems) was used in the simulations. The power amplifiers showed noise figure as low as 0.064dbs for class A, and 0.32 dbs for class B, and 0.69 dbs for class AB power amplifiers. The design was stable and as high as 5.12 for class A, 1.02 for class B, and 1.014 for class AB. The stability factor was estimated at 2GHz operation. The harmonics were as low as -100 dbs for class A, -60 dbs for class B, and -50dbs for class AB, all simulated at 1GHz. The device was incorporated into ADC system, and as low as 24.5 micro Watt power consumption and 40 nsec rise time were observed. Likewise, the DAC showed low power consumption as of 4.51 micro Watt. The serializer showed as minimum power consumption of the order of 0.4mW. These results showed that these nanoscale devices have potential future for high-speed communication systems, medical devices, computer architecture and dynamic Nano electromechanical (NEMS) which provides ultra-level of integration, incorporating embedded and IoT devices supporting this technology. Results of analog and digital components showed superiority over other silicon transistor technologies in their ultra-low power consumption and high switching speed.
  • Thumbnail Image
    Item
    A Process for Hybrid Superconducting and Graphene Devices
    (2021-05) Cochran, Zachary; Rizkalla, Maher; Ytterdal, Trond; Christopher, Lauren
    As the search for ever-higher-speed, greater-density, and lower-power technologies accelerates, so does the quest for devices and methodologies to fulfill the increasingly-difficult requirements for these technologies. A possible means by which this may be accomplished is to utilize superconducting devices and graphene nanoribbon nanotechnologies. This is because superconductors are ultra-low-power devices capable of generating extremely high frequency (EHF) signals, and graphene nanoribbons are nanoscale devices capable of extremely high-speed and low-power signal amplification due to their high-mobility/low-resistance channels and geometry-dependent bandgap structure. While such a hybrid co-integrated system seems possible, no process by which this may be accomplished has yet been proposed. In this thesis, the system limitations are explored in-depth, and several possible means by which superconducting and graphene nanotechnological systems may be united are proposed, with the focus being placed on the simplest method by which the technologies may be hybridized and integrated together, while maintaining control over the intended system behavior. This is accomplished in three parts. First, via circuit-level simulation, a semi-optimized, low-power (~0.21 mW/stage) graphene-based amplifier is developed using ideal and simplified transmission line properties. This system is theoretically capable of 159-269 GHz bandwidth with a Stern stability K >> 1 and low noise figure 2.97 <= F <= 4.33 dB for all appropriate frequencies at temperatures between 77 and 90 K. Second, an investigation of the behavior of several types of possible interconnect methodologies is performed, utilizing hybrid substrates and material interfaces/junctions, demonstrating that an Ohmic-contact superconducting-normal transmission line is optimal for a hybrid system with self-reflections at less than -25 dB over an operating range of 300 GHz. Finally, a unified layout and lithography construction process is proposed by which such a hybrid system could be developed in a monolithic physical system on a hybrid substrate while maintaining material and layout integrity under varying process temperatures.