Browsing by Subject "Embedded Systems"

Now showing 1 - 3 of 3
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    Embedded System for Sensor Communication and Security
    (2010) An, Feng; Rizkalla, Maher; Li, Lingxi; Du, Yingzi; Salama, Paul; Knieser, Michael
    In this work, inter-integrated circuit mode (I2C) software was used to communicate between sensors and the embedded control system, utilizing PIC182585 MPLAB hardware. These sensors were built as part of a system on board that includes the sensors, microcontroller, and interface circuitry. The hardware includes the PIC18 processor, FPGA chip, and peripherals. A FPGA chip was used to interface the processor with the peripherals in order to operate at the same clock speed. This hardware design features high level of integration, reliability, high precision, and high speed communications. The software was first designed to operate each sensor separately, then the sensor system was integrated (to combine all sensors, microcontroller, and interfacing circuitries), and the software was updated to provide various actions if triggered by the sensors. Actions taken by the processor may include alarming signals that are based on threshold values received from the sensors, and inquiring temperature and CO2 readings. The system was designed for HVAC (heating, ventilating and air conditioning) applications and industrial settings. The overall system incorporating temperature and CO2 sensors was implemented and successfully tested. The response of the multi-sensor system was agreeable with the design parameters. The system may be expanded to include other sensors such as light senor, pressure sensor, etc. Monitoring the threshold values should add to the security features of the integrated communication system. This design features low power consumption (utilizing the sleeping mode of the processors), high speed communications, security, and flexibility to expansion.
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    HBONext: An Efficient Dnn for Light Edge Embedded Devices
    (2021-05) Joshi, Sanket Ramesh; El-Sharkawy, Mohamed; King, Brian; Rizkalla, Maher
    Every year the most effective Deep learning models, CNN architectures are showcased based on their compatibility and performance on the embedded edge hardware, especially for applications like image classification. These deep learning models necessitate a significant amount of computation and memory, so they can only be used on high-performance computing systems like CPUs or GPUs. However, they often struggle to fulfill portable specifications due to resource, energy, and real-time constraints. Hardware accelerators have recently been designed to provide the computational resources that AI and machine learning tools need. These edge accelerators have high-performance hardware which helps maintain the precision needed to accomplish this mission. Furthermore, this classification dilemma that investigates channel interdependencies using either depth-wise or group-wise convolutional features, has benefited from the inclusion of Bottleneck modules. Because of its increasing use in portable applications, the classic inverted residual block, a well-known architecture technique, has gotten more recognition. This work takes it a step forward by introducing a design method for porting CNNs to lowresource embedded systems, essentially bridging the difference between deep learning models and embedded edge systems. To achieve these goals, we use closer computing strategies to reduce the computer’s computational load and memory usage while retaining excellent deployment efficiency. This thesis work introduces HBONext, a mutated version of Harmonious Bottlenecks (DHbneck) combined with a Flipped version of Inverted Residual (FIR), which outperforms the current HBONet architecture in terms of accuracy and model size miniaturization. Unlike the current definition of inverted residual, this FIR block performs identity mapping and spatial transformation at its higher dimensions. The HBO solution, on the other hand, focuses on two orthogonal dimensions: spatial (H/W) contraction-expansion and later channel (C) expansion-contraction, which are both organized in a bilaterally symmetric manner. HBONext is one of those versions that was designed specifically for embedded and mobile applications. In this research work, we also show how to use NXP Bluebox 2.0 to build a real-time HBONext image classifier. The integration of the model into this hardware has been a big hit owing to the limited model size of 3 MB. The model was trained and validated using CIFAR10 dataset, which performed exceptionally well due to its smaller size and higher accuracy. The validation accuracy of the baseline HBONet architecture is 80.97%, and the model is 22 MB in size. The proposed architecture HBONext variants, on the other hand, gave a higher validation accuracy of 89.70% and a model size of 3.00 MB measured using the number of parameters. The performance metrics of HBONext architecture and its various variants are compared in the following chapters.
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    MSTE Flywheel Capstone Project Report
    (2024-04-30) Hill, Kaleb; Franco, Gabrielle; Abegunde, Dami; Weissbach, Robert; Pash, Phillip; Freije, Elizabeth
    The objective of this capstone project evolved during its progression, ultimately aiming to develop a control system capable of idling the engine and operating the flywheel with braking capabilities. The flywheel's functionality includes idling the engine at approximately 3000-5000 RPM and rotating at speeds between 7000-9000 RPM. While the complete control system remains a work in progress, the flywheel can be fully braked, and preliminary data analysis has been conducted. Presently, the servo mechanism is utilized to maintain engine idling, adjusting the throttle to approximately 108° and returning to 100° upon closure. Future iterations will involve further servo implementation to facilitate RPM acceleration, achieving full throttle opening at 120° and introduce gradual braking.