IU Indianapolis ScholarWorks :: Browsing by Author "Ytterdal, Trond"

Browsing by Author "Ytterdal, Trond"

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GNRFET-Based DC-DC Converters for Low Power Data Management in ULSI System, a Feasibility Study
(IEEE, 2021) Mekhael, George; Morgan, Nathaniel; Patnala, Mounica; Ytterdal, Trond; Rizkalla, Maher; Electrical and Computer Engineering, School of Engineering and Technology
Low power data management is an approach that distribute the supply power on the various modules in the chip, following certain algorithms such as dynamic voltage sharing (DVS), single input multiple data (SIMD) among others with a coil-less circuit design. The key factors for reducing the power and enhancing the efficiency is attributed to the lower feeding power supply, high device mobility for low power consumption, the device size, and the architecture used in the design. Graphene Nano Ribbon Field Effect Transistors (GNRFET) based Buck and Boost converters were designed for single input/multiple outputs conversion. The design features very high efficiency that exceeds 90% at very high frequencies. The input was 0.7V with outputs of 0.35V and 1.4V for buck and boost converters respectively. The design gains from the high mobility feature of the nano scale GNRFET devices, and the low supply power applied to the various modules in the chip. A 10nm scale channel device with 4 ribbons were considered, and the switch capacitor (SC) approach was utilized. The study of the transient analysis, the static power, dynamic power, and ripple voltages at different design constraints were investigated versus the conversion parameters including the frequency, load, and duty cycles. The efficiency at a high load was estimated to be near 97%, while at low load and lower switching frequencies, the efficiency was estimated to be near 85%.
High Performance GNRFET Devices for High-Speed Low-Power Analog and Digital Applications
(2019-05) Patnala, Mounica; Rizkalla, Maher E.; King, Brian S.; Sharkawy, Mohamed El; Ytterdal, Trond
Recent ULSI (ultra large scale integration) technology emphasizes small size devices, featuring low power and high switching speed. Moore's law has been followed successfully in scaling down the silicon device in order to enhance the level of integration with high performances until conventional devices failed to cop up with further scaling due to limitations with ballistic effects, and challenges with accommodating dopant fluctuation, mobility degradation, among other device parameters. Recently, Graphene based devices o ered alternative approach, featuring small size and high performances. This includes high carrier mobility, high carrier density, high robustness, and high thermal conductivity. These unique characteristics made the Graphene devices attractive for high speed electronic architectures. In this research, Graphene devices were integrated into applications with analog, digital, and mixed signals based systems. Graphene devices were briefly explored in electronics applications since its first model developed by the University of Illinois, Champaign in 2013. This study emphasizes the validation of the model in various applications with analog, digital, and mixed signals. At the analog level, the model was used for voltage and power amplifiers; classes A, B, and AB. At the digital level, the device model was validated within the universal gates, adders, multipliers, subtractors, multiplexers, demultiplexers, encoders, and comparators. The study was also extended to include Graphene devices for serializers, the digital systems incorporated into the data structure storage. At the mixed signal level, the device model was validated for the DACs/ADCs. In all components, the features of the new devices were emphasized as compared with the existing silicon technology. The system functionality and dynamic performances were also elaborated. The study also covered the linearity characteristics of the devices within full input range operation. GNRFETs with a minimum channel length of 10nm and an input voltage 0.7V were considered in the study. An electronic design platform ADS (Advanced Design Systems) was used in the simulations. The power amplifiers showed noise figure as low as 0.064dbs for class A, and 0.32 dbs for class B, and 0.69 dbs for class AB power amplifiers. The design was stable and as high as 5.12 for class A, 1.02 for class B, and 1.014 for class AB. The stability factor was estimated at 2GHz operation. The harmonics were as low as -100 dbs for class A, -60 dbs for class B, and -50dbs for class AB, all simulated at 1GHz. The device was incorporated into ADC system, and as low as 24.5 micro Watt power consumption and 40 nsec rise time were observed. Likewise, the DAC showed low power consumption as of 4.51 micro Watt. The serializer showed as minimum power consumption of the order of 0.4mW. These results showed that these nanoscale devices have potential future for high-speed communication systems, medical devices, computer architecture and dynamic Nano electromechanical (NEMS) which provides ultra-level of integration, incorporating embedded and IoT devices supporting this technology. Results of analog and digital components showed superiority over other silicon transistor technologies in their ultra-low power consumption and high switching speed.
A Low Power FinFET Charge Pump For Energy Harvesting Applications
(2020-05) Whittaker, Kyle; Rizkalla, Maher E.; Ytterdal, Trond; King, Brian S.
With the growing popularity and use of devices under the great umbrella that is the Internet of Things (IoT), the need for devices that are smaller, faster, cheaper and require less power is at an all time high with no intentions of slowing down. This is why many current research efforts are very focused on energy harvesting. Energy harvesting is the process of storing energy from external and ambient sources and delivering a small amount of power to low power IoT devices such as wireless sensors or wearable electronics. A charge pumps is a circuit used to convert a power supply to a higher or lower voltage depending on the specific application. Charge pumps are generally seen in memory design as a verity of power supplies are required for the newer memory technologies. Charge pumps can be also be designed for low voltage operation and can convert a smaller energy harvesting voltage level output to one that may be needed for the IoT device to operate. In this work, an integrated FinFET (Field Effect Transistor) charge pump for low power energy harvesting applications is proposed. The design and analysis of this system was conducted using Cadence Virtuoso Schematic L-Editing, Analog Design Environment and Spectre Circuit Simulator tools using the 7nm FinFETs from the ASAP7 7nm PDK. The research conducted here takes advantage of some inherent characteristics that are present in FinFET technologies, including low body effects, and faster switching speeds, lower threshold voltage and lower power consumption. The lower threshold voltage of the FinFET is key to get great performance at lower supply voltages. The charge pump in this work is designed to pump a 150mV power supply, generated from an energy harvester, to a regulated 650mV, while supplying 1uA of load current, with a 20mV voltage ripple in steady state (SS) operation. At these conditions, the systems power consumption is 4.85uW and is 31.76% efficient. Under no loading conditions, the charge pump reaches SS operation in 50us, giving it the fastest rise time of the compared state of the art efforts mentioned in this work. The minimum power supply voltage for the system to function is 93mV where it gives a regulated output voltage of $25mV. FinFET technology continues to be a very popular design choice and even though it has been in production since Intel's Ivy-Bridge processor in 2012, it seems that very few efforts have been made to use the advantages of FinFETs for charge pump design. This work shows though simulation that FinFET charge pumps can match the performance of charge pumps implemented in other technologies and should be considered for low power designs such as energy harvesting.
Multi-Threshold Low Power-Delay Product Memory and Datapath Components Utilizing Advanced FinFET Technology Emphasizing the Reliability and Robustness
(2020-12) Yadav, Avinash; Rizkalla, Maher E.; Ytterdal, Trond; Lee, John J.
In this thesis, we investigated the 7 nm FinFET technology for its delay-power product performance. In our study, we explored the ASAP7 library from Arizona State University, developed in collaboration with ARM Holdings. The FinFET technology was chosen since it has a subthreshold slope of 60mV/decade that enables cells to function at 0.7V supply voltage at the nominal corner. An emphasis was focused on characterizing the Non-Ideal effects, delay variation, and power for the FinFET device. An exhaustive analysis of the INVx1 delay variation for different operating conditions was also included, to assess the robustness. The 7nm FinFET device was then employed into 6T SRAM cells and 16 function ALU. The SRAM cells were approached with advanced multi-corner stability evaluation. The system-level architecture of the ALU has demonstrated an ultra-low power system operating at 1 GHz clock frequency.
A Process for Hybrid Superconducting and Graphene Devices
(2021-05) Cochran, Zachary; Rizkalla, Maher; Ytterdal, Trond; Christopher, Lauren
As the search for ever-higher-speed, greater-density, and lower-power technologies accelerates, so does the quest for devices and methodologies to fulfill the increasingly-difficult requirements for these technologies. A possible means by which this may be accomplished is to utilize superconducting devices and graphene nanoribbon nanotechnologies. This is because superconductors are ultra-low-power devices capable of generating extremely high frequency (EHF) signals, and graphene nanoribbons are nanoscale devices capable of extremely high-speed and low-power signal amplification due to their high-mobility/low-resistance channels and geometry-dependent bandgap structure. While such a hybrid co-integrated system seems possible, no process by which this may be accomplished has yet been proposed. In this thesis, the system limitations are explored in-depth, and several possible means by which superconducting and graphene nanotechnological systems may be united are proposed, with the focus being placed on the simplest method by which the technologies may be hybridized and integrated together, while maintaining control over the intended system behavior. This is accomplished in three parts. First, via circuit-level simulation, a semi-optimized, low-power (~0.21 mW/stage) graphene-based amplifier is developed using ideal and simplified transmission line properties. This system is theoretically capable of 159-269 GHz bandwidth with a Stern stability K >> 1 and low noise figure 2.97 <= F <= 4.33 dB for all appropriate frequencies at temperatures between 77 and 90 K. Second, an investigation of the behavior of several types of possible interconnect methodologies is performed, utilizing hybrid substrates and material interfaces/junctions, demonstrating that an Ohmic-contact superconducting-normal transmission line is optimal for a hybrid system with self-reflections at less than -25 dB over an operating range of 300 GHz. Finally, a unified layout and lithography construction process is proposed by which such a hybrid system could be developed in a monolithic physical system on a hybrid substrate while maintaining material and layout integrity under varying process temperatures.
Robust, Enhanced-Performance SRAMs via Nanoscale CMOS and Beyond-CMOS Technologies
(2022-12) Gopinath, Anoop; Rizkalla, Maher E.; Ytterdal, Trond; Lee, John J.; Kumar, Mukesh; King, Brian S.
In this dissertation, a beyond-CMOS approach to Static Random Access Memory (SRAM) design is investigated using exploratory transistors including Tunnel Field Effect Transistor (TFET), Carbon Nanotube Field Effect Transistor (CNFET) and Graphene NanoRibbon Field Effect Transistor (GNRFET). A Figure-of-Merit (FOM) based comparison of 6-transistor (6T) and a modified 8-transistor (8T) single-port SRAMs designed using exploratory devices, and contemporary devices such as a FinFET and a CMOS process, highlighted the performance benefits of GNRFETs and power benefits of TFETs. The results obtained from the this work show that GNRFET-based SRAM have very high performance with a worst-case memory access time of 27.7 ps for a 16x4-bit 4-word array of 256-bitcells. CNFET-based SRAM bitcell consume the lowest average power during read/write simulations at 3.84 uW, while TFET-based SRAM bitcell show the best overall average and static power consumption at 4.79 uW and 57.8 pW respectively. A comparison of these exploratory devices with FinFET and planar CMOS showed that FinFET-based SRAM bitcell consumed the lowest static power at 39.8 pW and CMOS-based SRAM had the best read, write and hold static noise margins at 201 mV, 438 mV and 413 mV respectively. Further, the modification of 8T-SRAMs via dual wordlines for individually controlling read and write operations for uni-directional transistors TFET and CNFET show improvement in read static noise margin (RSNM). In dual wordline CNFET 8T-SRAM, an RSNM improvement of approximately 23.6x from 6 mV to 142 mV was observed by suppressing the read wordline (RWL) from a nominal supply of 0.71 V down to 0.61 V. In dual wordline TFET 8T-SRAM, an RSNM improvement of approximately 16.2x from 5 mV to 81 mV was observed by suppressing the RWL from a nominal supply of 0.6 V down to 0.3 V. Next, the dissertation explores whether the robustness of SRAM arrays can be improved. Specifically, the robustness related to noise margin during the write operation was investigated by implementing a negative bitline (NBL) voltage scheme. NBL improves the write static noise margin (WSNM) of the SRAM bitcells in the row of the array to which the data is written during a write operation. However, this may cause degraded hold static noise margin (HSNM) of un-accessed cells in the array. Applying a negative wordline voltage (NWL) on un-accessed cells during NBL shows that the NWL can counter the degraded HSNM of un-accessed cells due to NBL. The scheme, titled as NBLWL, also allows the supply of a lower NBL, resulting in higher WSNM and write-ability benefits of accessed row. By applying a complementary negative wordline voltage to counter the half-select condition in columns, the WSNM of cells in accessed rows was boosted by 10.9% when compared to a work where no negative bitline was applied. In addition, the HSNM of un-accessed cells remain the same as in the case where no negative bitline was implemented. Essentially, a 10.9% boost in WSNM without any degradation of HSNM in un-accessed cells is observed. The dissertation also focuses on the impact of process-related variations in SRAM arrays to correlate and characterize silicon data to simulation data. This can help designers remove pessimistic margins that are placed on critical signals to account for expected process variation. Removing these pessimistic margins on critical data paths that dictate the memory access time results in performance benefits for the SRAM array. This is achieved via an in-situ silicon monitor titled SRAM process and ageing sensor (SPAS), which can be used for silicon and ageing characterization, and silicon debug. The SPAS scheme is based on a process variation tolerant technique called RAZOR that compares the data arriving on the output of the sense amplifiers during the read operation. This scheme can estimate the impact of process variation and ageing induced slow-down on critical path during read operation of an array with high accuracy. The estimation accuracy in a commercially available 65nm CMOS technology for a 16x16 array at TT, and global SS and FF corners at nominal supply and testing temperature were found to be 99.2%, 94.9% and 96.5% respectively. Finally, redundant columns, an architectural-level scheme for tolerating failing SRAM bitcells in arrays without compromising performance and yield, is studied. Redundant columns are extra columns that are programmed when bitcells in the regular columns of an array are slower or have higher leakage than expected post-silicon. The regular columns are often permanently disabled and remain unused for the chip lifetime once redundant columns are enabled. In the SRRC scheme proposed in this thesis, the regular columns are only temporarily disabled, and re-used at a later time in chip life cycle once the previously awakened redundant columns become slower than the disabled regular columns. Essentially, the scheme can identify and temporarily disable the slowest column in an array until other mitigating factors slow down active columns. This allows the array to operate at a memory access time closer to the target access time regardless of other mitigating factors slowing down bitcells in arrays during chip life cycle. An approximate 76.4% reduction in memory access time was observed from a 16x16 array from simulations in a commercially available 65nm CMOS technology with respect to a work where no redundancy was employed.
SRAM design leveraging material properties of exploratory transistors
(Elsevier, 2022) Gopinath, Anoop; Cochran, Zachary; Ytterdal, Trond; Rizkalla, Maher; Electrical and Computer Engineering, Purdue School of Engineering and Technology
While MOSFET miniaturization continues to face increased challenges related to process variations, supply voltage scaling and leakage currents, exploratory devices such as Graphene Nanoribbon Field Effect Transistors (GNRFET), Tunnel Field Effect Transistor (TFET), and Carbon Nanotube Field Effects Transistors (CNFET) could provide solutions for continued device scaling with better power/performance trade-offs. The GaN TFET used in this work is a heterojunction device, where the material properties of Ga and N result in a bandgap of 3.2eV and ultra-low IOFF current. Moreover, the properties of Ga and N result in a steep-switching device with a subthreshold swing of 30mV/decade. The structure of graphene material results in high conductivity of electrons, even at very high operating temperatures, making GNRFETs a high-performance device. However, graphene specific line-edge roughness can degrade performance, and thus process related variations can have a negative impact for GNRFETs. In CNFETs, the mobility and the velocity of the conducting carriers are functions of the carbon nanotube and the gate length. The length and the diameter of the carbon nanotube material adds parasitic capacitance and resistance to the model, contributing to slower speed of the device. In this paper, the impact on power, performance, and static noise margins (SNM) of the traditional single-port 6T-SRAM and modified single-port 8T-SRAMs designed using exploratory devices are analyzed with a set figure of merit (FOM), elucidating the material properties of the devices. The results obtained from this work show that GNRFET-based SRAM have very high performance with a worst-case memory access time of 27.7 ps for a 16x4-bit 4-word array while CNFET-based SRAM bitcell consume the lowest average power during read/write simulations at 3.84 µW, while TFET- based SRAM bitcell show the best overall average and static power consumption at 4.79 µW and 57.8 pW. A comparison of these exploratory devices with FinFET and planar CMOS showed that FinFET-based SRAM bitcell consumed the lowest static power at 39.8 pW and CMOS-based SRAM had the best read, write, and hold SNMs of 201 mV, 438 mV and 413 mV respectively.
Towards No-Penalty Control Hazard Handling in RISC Architecture Microcontrollers
(2024-08) Balasubramanian, Linknath Surya; Rizkalla, Maher E.; Lee, John J.; Ytterdal, Trond; Kumar, Mukesh
Achieving higher throughput is one of the most important requirements of a modern microcontroller. It is therefore not affordable for it to waste a considerable number of clock cycles in branch mispredictions. This paper proposes a hardware mechanism that makes microcontrollers forgo branch predictors, thereby removing branch mispredictions. The scope of this work is limited to low cost microcontroller cores that are applied in embedded systems. The proposed technique is implemented as five different modules which work together to forward required operands, resolve branches without prediction, and calculate the next instruction's address in the first stage of an in-order five stage pipelined micro-architecture. Since the address of successive instruction to a control transfer instruction is calculated in the first stage of pipeline, branch prediction is no longer necessary, thereby eliminating the clock cycle penalties occurred when using a branch predictor. The designed architecture was able to successfully calculate the address of next correct instruction and fetch it without any wastage of clock cycles except in cases where control transfer instructions are in true dependence with their immediate previous instructions. Further, we synthesized the proposed design with 7nm FinFET process and compared its latency with other designs to make sure that the microcontroller's operating frequency is not degraded by using this design. The critical path latency of instruction fetch stage integrated with the proposed architecture is 307 ps excluding the instruction cache access time.

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