Browsing by Author "Patnala, Mounica"

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    Eletromagnetic Detection of Mild Brain Injury: A Novel Imaging Approach to Post Concussive Syndrome
    (Scientific Research Publishing, 2021-11) Rizkalla, James; Botros, David; Alqahtani, Nasser; Patnala, Mounica; Salama, Paul; Perez, Felipe Pablo; Rizkalla, Maher; Medicine, School of Medicine
    Introduction: Mild traumatic brain injury (mTBI) is a common injury, with nearly 3 - 4 million cases annually in the United States alone. Neuroimaging in patients with mTBI provides little benefit, and is usually not indicated as the diagnosis is primarily clinical. It is theorized that microvascular trauma to the brain may be present in mTBI, that may not be captured by routine MRI and CT scans. Electromagnetic (EM) waves may provide a more sensitive medical imaging modality to provide objective data in the diagnosis of mTBI. Methods: COMSOL simulation software was utilized to mimic the anatomy of the human skull including skin, cranium, cerebrospinal fluid (CSF), gray-matter tissue of the brain, and microvasculature within the neural tissue. The effects of penetrating EM waves were simulated using the finite element analysis software and results were generated to identify feasibility and efficacy. Frequency ranges from 7 GHz to 15 GHz were considered, with 0.6 and 1 W power applied. Results: Variations between the differing frequency levels generated different energy levels within the neural tissue-particularly when comparing normal microvasculature versus hemorrhage from microvasculature. This difference within the neural tissue was subsequently identified, via simulation, serving as a potential imaging modality for future work. Conclusion: The use of electromagnetic imaging of the brain after concussive events may play a role in future mTBI diagnosis. Utilizing the proper depth frequency and wavelength, neural tissue and microvascular trauma may be identified utilizing finite element analysis.
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    GNRFET-Based DC-DC Converters for Low Power Data Management in ULSI System, a Feasibility Study
    (IEEE, 2021) Mekhael, George; Morgan, Nathaniel; Patnala, Mounica; Ytterdal, Trond; Rizkalla, Maher; Electrical and Computer Engineering, School of Engineering and Technology
    Low power data management is an approach that distribute the supply power on the various modules in the chip, following certain algorithms such as dynamic voltage sharing (DVS), single input multiple data (SIMD) among others with a coil-less circuit design. The key factors for reducing the power and enhancing the efficiency is attributed to the lower feeding power supply, high device mobility for low power consumption, the device size, and the architecture used in the design. Graphene Nano Ribbon Field Effect Transistors (GNRFET) based Buck and Boost converters were designed for single input/multiple outputs conversion. The design features very high efficiency that exceeds 90% at very high frequencies. The input was 0.7V with outputs of 0.35V and 1.4V for buck and boost converters respectively. The design gains from the high mobility feature of the nano scale GNRFET devices, and the low supply power applied to the various modules in the chip. A 10nm scale channel device with 4 ribbons were considered, and the switch capacitor (SC) approach was utilized. The study of the transient analysis, the static power, dynamic power, and ripple voltages at different design constraints were investigated versus the conversion parameters including the frequency, load, and duty cycles. The efficiency at a high load was estimated to be near 97%, while at low load and lower switching frequencies, the efficiency was estimated to be near 85%.
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    High Performance GNRFET Devices for High-Speed Low-Power Analog and Digital Applications
    (2019-05) Patnala, Mounica; Rizkalla, Maher E.; King, Brian S.; Sharkawy, Mohamed El; Ytterdal, Trond
    Recent ULSI (ultra large scale integration) technology emphasizes small size devices, featuring low power and high switching speed. Moore's law has been followed successfully in scaling down the silicon device in order to enhance the level of integration with high performances until conventional devices failed to cop up with further scaling due to limitations with ballistic effects, and challenges with accommodating dopant fluctuation, mobility degradation, among other device parameters. Recently, Graphene based devices o ered alternative approach, featuring small size and high performances. This includes high carrier mobility, high carrier density, high robustness, and high thermal conductivity. These unique characteristics made the Graphene devices attractive for high speed electronic architectures. In this research, Graphene devices were integrated into applications with analog, digital, and mixed signals based systems. Graphene devices were briefly explored in electronics applications since its first model developed by the University of Illinois, Champaign in 2013. This study emphasizes the validation of the model in various applications with analog, digital, and mixed signals. At the analog level, the model was used for voltage and power amplifiers; classes A, B, and AB. At the digital level, the device model was validated within the universal gates, adders, multipliers, subtractors, multiplexers, demultiplexers, encoders, and comparators. The study was also extended to include Graphene devices for serializers, the digital systems incorporated into the data structure storage. At the mixed signal level, the device model was validated for the DACs/ADCs. In all components, the features of the new devices were emphasized as compared with the existing silicon technology. The system functionality and dynamic performances were also elaborated. The study also covered the linearity characteristics of the devices within full input range operation. GNRFETs with a minimum channel length of 10nm and an input voltage 0.7V were considered in the study. An electronic design platform ADS (Advanced Design Systems) was used in the simulations. The power amplifiers showed noise figure as low as 0.064dbs for class A, and 0.32 dbs for class B, and 0.69 dbs for class AB power amplifiers. The design was stable and as high as 5.12 for class A, 1.02 for class B, and 1.014 for class AB. The stability factor was estimated at 2GHz operation. The harmonics were as low as -100 dbs for class A, -60 dbs for class B, and -50dbs for class AB, all simulated at 1GHz. The device was incorporated into ADC system, and as low as 24.5 micro Watt power consumption and 40 nsec rise time were observed. Likewise, the DAC showed low power consumption as of 4.51 micro Watt. The serializer showed as minimum power consumption of the order of 0.4mW. These results showed that these nanoscale devices have potential future for high-speed communication systems, medical devices, computer architecture and dynamic Nano electromechanical (NEMS) which provides ultra-level of integration, incorporating embedded and IoT devices supporting this technology. Results of analog and digital components showed superiority over other silicon transistor technologies in their ultra-low power consumption and high switching speed.