Browsing by Author "Gopinath, Anoop"

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    Low-power hybrid TFET-CMOS memory
    (2018-04-02) Gopinath, Anoop; Rizkalla, Maher E.
    Gopinath, Anoop. M.S.E.C.E., Purdue University, May 2018. Low-Power Hybrid TFET-CMOS Memory. Major Professor: Maher E. Rizkalla. The power consumption and the switching speed of the current CMOS technology have reached their limits. In contrast, architecture design within computer systems are continuously seeking more performance and e ciency. Advanced technologies that optimize the power consumption and switching speed may help deliver this e ciency. Indeed, beyond CMOS technology may be a viable approach to meeting the ever increasing need for low-power design. These technology includes devices such as Tunnel Field E ect Transistor (TFET), Graphene based devices such as GFET and GRNFET and FinFET. However, the low cross-sectional area of the channel asso- ciated with smaller technology nodes brings with it the challenges associated with leakage current below the threshold. Mitigating these challenges with devices such as TFETs may allow higher levels of integration, faster switching speed and lower power consumption. This thesis investigates the use of Gallium Nitride (GaN) TFET devices at 20nm for memory cells. These cells can be used in the L1 data cache of the Graphic Processing Units (GPU) thereby minimizing the static power and the dynamic power within these memory systems. The TFET technology was chosen since it has a low subthreshold slope of nearly 30mV/decade. This enables the TFET-based cells to function with a 0.6V supply voltage leading to reduced dynamic power consumption and leakage current when compared to the current CMOS technology. The results suggest that there are bene ts in pursuing an integrated TFET-based technology for Very Large Scale Integrated Circuit (VLSI) design. These bene ts are demonstrated using simulation at the schematic-level using Cadence Virtuoso.
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    Robust, Enhanced-Performance SRAMs via Nanoscale CMOS and Beyond-CMOS Technologies
    (2022-12) Gopinath, Anoop; Rizkalla, Maher E.; Ytterdal, Trond; Lee, John J.; Kumar, Mukesh; King, Brian S.
    In this dissertation, a beyond-CMOS approach to Static Random Access Memory (SRAM) design is investigated using exploratory transistors including Tunnel Field Effect Transistor (TFET), Carbon Nanotube Field Effect Transistor (CNFET) and Graphene NanoRibbon Field Effect Transistor (GNRFET). A Figure-of-Merit (FOM) based comparison of 6-transistor (6T) and a modified 8-transistor (8T) single-port SRAMs designed using exploratory devices, and contemporary devices such as a FinFET and a CMOS process, highlighted the performance benefits of GNRFETs and power benefits of TFETs. The results obtained from the this work show that GNRFET-based SRAM have very high performance with a worst-case memory access time of 27.7 ps for a 16x4-bit 4-word array of 256-bitcells. CNFET-based SRAM bitcell consume the lowest average power during read/write simulations at 3.84 uW, while TFET-based SRAM bitcell show the best overall average and static power consumption at 4.79 uW and 57.8 pW respectively. A comparison of these exploratory devices with FinFET and planar CMOS showed that FinFET-based SRAM bitcell consumed the lowest static power at 39.8 pW and CMOS-based SRAM had the best read, write and hold static noise margins at 201 mV, 438 mV and 413 mV respectively. Further, the modification of 8T-SRAMs via dual wordlines for individually controlling read and write operations for uni-directional transistors TFET and CNFET show improvement in read static noise margin (RSNM). In dual wordline CNFET 8T-SRAM, an RSNM improvement of approximately 23.6x from 6 mV to 142 mV was observed by suppressing the read wordline (RWL) from a nominal supply of 0.71 V down to 0.61 V. In dual wordline TFET 8T-SRAM, an RSNM improvement of approximately 16.2x from 5 mV to 81 mV was observed by suppressing the RWL from a nominal supply of 0.6 V down to 0.3 V. Next, the dissertation explores whether the robustness of SRAM arrays can be improved. Specifically, the robustness related to noise margin during the write operation was investigated by implementing a negative bitline (NBL) voltage scheme. NBL improves the write static noise margin (WSNM) of the SRAM bitcells in the row of the array to which the data is written during a write operation. However, this may cause degraded hold static noise margin (HSNM) of un-accessed cells in the array. Applying a negative wordline voltage (NWL) on un-accessed cells during NBL shows that the NWL can counter the degraded HSNM of un-accessed cells due to NBL. The scheme, titled as NBLWL, also allows the supply of a lower NBL, resulting in higher WSNM and write-ability benefits of accessed row. By applying a complementary negative wordline voltage to counter the half-select condition in columns, the WSNM of cells in accessed rows was boosted by 10.9% when compared to a work where no negative bitline was applied. In addition, the HSNM of un-accessed cells remain the same as in the case where no negative bitline was implemented. Essentially, a 10.9% boost in WSNM without any degradation of HSNM in un-accessed cells is observed. The dissertation also focuses on the impact of process-related variations in SRAM arrays to correlate and characterize silicon data to simulation data. This can help designers remove pessimistic margins that are placed on critical signals to account for expected process variation. Removing these pessimistic margins on critical data paths that dictate the memory access time results in performance benefits for the SRAM array. This is achieved via an in-situ silicon monitor titled SRAM process and ageing sensor (SPAS), which can be used for silicon and ageing characterization, and silicon debug. The SPAS scheme is based on a process variation tolerant technique called RAZOR that compares the data arriving on the output of the sense amplifiers during the read operation. This scheme can estimate the impact of process variation and ageing induced slow-down on critical path during read operation of an array with high accuracy. The estimation accuracy in a commercially available 65nm CMOS technology for a 16x16 array at TT, and global SS and FF corners at nominal supply and testing temperature were found to be 99.2%, 94.9% and 96.5% respectively. Finally, redundant columns, an architectural-level scheme for tolerating failing SRAM bitcells in arrays without compromising performance and yield, is studied. Redundant columns are extra columns that are programmed when bitcells in the regular columns of an array are slower or have higher leakage than expected post-silicon. The regular columns are often permanently disabled and remain unused for the chip lifetime once redundant columns are enabled. In the SRRC scheme proposed in this thesis, the regular columns are only temporarily disabled, and re-used at a later time in chip life cycle once the previously awakened redundant columns become slower than the disabled regular columns. Essentially, the scheme can identify and temporarily disable the slowest column in an array until other mitigating factors slow down active columns. This allows the array to operate at a memory access time closer to the target access time regardless of other mitigating factors slowing down bitcells in arrays during chip life cycle. An approximate 76.4% reduction in memory access time was observed from a 16x16 array from simulations in a commercially available 65nm CMOS technology with respect to a work where no redundancy was employed.
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    SRAM design leveraging material properties of exploratory transistors
    (Elsevier, 2022) Gopinath, Anoop; Cochran, Zachary; Ytterdal, Trond; Rizkalla, Maher; Electrical and Computer Engineering, Purdue School of Engineering and Technology
    While MOSFET miniaturization continues to face increased challenges related to process variations, supply voltage scaling and leakage currents, exploratory devices such as Graphene Nanoribbon Field Effect Transistors (GNRFET), Tunnel Field Effect Transistor (TFET), and Carbon Nanotube Field Effects Transistors (CNFET) could provide solutions for continued device scaling with better power/performance trade-offs. The GaN TFET used in this work is a heterojunction device, where the material properties of Ga and N result in a bandgap of 3.2eV and ultra-low IOFF current. Moreover, the properties of Ga and N result in a steep-switching device with a subthreshold swing of 30mV/decade. The structure of graphene material results in high conductivity of electrons, even at very high operating temperatures, making GNRFETs a high-performance device. However, graphene specific line-edge roughness can degrade performance, and thus process related variations can have a negative impact for GNRFETs. In CNFETs, the mobility and the velocity of the conducting carriers are functions of the carbon nanotube and the gate length. The length and the diameter of the carbon nanotube material adds parasitic capacitance and resistance to the model, contributing to slower speed of the device. In this paper, the impact on power, performance, and static noise margins (SNM) of the traditional single-port 6T-SRAM and modified single-port 8T-SRAMs designed using exploratory devices are analyzed with a set figure of merit (FOM), elucidating the material properties of the devices. The results obtained from this work show that GNRFET-based SRAM have very high performance with a worst-case memory access time of 27.7 ps for a 16x4-bit 4-word array while CNFET-based SRAM bitcell consume the lowest average power during read/write simulations at 3.84 µW, while TFET- based SRAM bitcell show the best overall average and static power consumption at 4.79 µW and 57.8 pW. A comparison of these exploratory devices with FinFET and planar CMOS showed that FinFET-based SRAM bitcell consumed the lowest static power at 39.8 pW and CMOS-based SRAM had the best read, write, and hold SNMs of 201 mV, 438 mV and 413 mV respectively.