Browsing by Author "Cochran, Zachary"

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    Enhancing Course Objectives for a Sophomore Electronic Devices Class via Peer-Led Team Learning (PLTL) Model and Attached Projects
    (IEEE, 2019-10) Shayesteh, Seemein; Cochran, Zachary; Dhavalikar, Raj; Huelsman, Ian; Madan, Akul; Peters, Taylor; Yago, Ahmed; Wible, Grant; Rizkalla, Maher; Electrical and Computer Engineering, School of Engineering and Technology
    This Full Innovative Practice paper presents a new Peer-Led team Learning (PLTL) recitation model for the sophomore Electronics Analysis and Design course, emphasizing device physics, device models, and analog and digital applications in the Department of Electrical and Computer Engineering at IUPUI. This new PLTL model with small number of students assigned to one peer-leader has enabled students to cooperate with each other and build teamwork, to get more practice with course software, and to better understand the course design component. This new model has overall improved the students' performance in the course. The new model has also enabled the instructor to introduce students to some research topics which led to students being encouraged to enroll in higher level related courses and to pursue further research in these areas. This paper details the structure of this new model, the feedback from students, the PLTL model recitation guidelines for the course semester, and attached projects. The paper also assesses the course objectives using this new model as compared to previous offerings.
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    A Process for Hybrid Superconducting and Graphene Devices
    (2021-05) Cochran, Zachary; Rizkalla, Maher; Ytterdal, Trond; Christopher, Lauren
    As the search for ever-higher-speed, greater-density, and lower-power technologies accelerates, so does the quest for devices and methodologies to fulfill the increasingly-difficult requirements for these technologies. A possible means by which this may be accomplished is to utilize superconducting devices and graphene nanoribbon nanotechnologies. This is because superconductors are ultra-low-power devices capable of generating extremely high frequency (EHF) signals, and graphene nanoribbons are nanoscale devices capable of extremely high-speed and low-power signal amplification due to their high-mobility/low-resistance channels and geometry-dependent bandgap structure. While such a hybrid co-integrated system seems possible, no process by which this may be accomplished has yet been proposed. In this thesis, the system limitations are explored in-depth, and several possible means by which superconducting and graphene nanotechnological systems may be united are proposed, with the focus being placed on the simplest method by which the technologies may be hybridized and integrated together, while maintaining control over the intended system behavior. This is accomplished in three parts. First, via circuit-level simulation, a semi-optimized, low-power (~0.21 mW/stage) graphene-based amplifier is developed using ideal and simplified transmission line properties. This system is theoretically capable of 159-269 GHz bandwidth with a Stern stability K >> 1 and low noise figure 2.97 <= F <= 4.33 dB for all appropriate frequencies at temperatures between 77 and 90 K. Second, an investigation of the behavior of several types of possible interconnect methodologies is performed, utilizing hybrid substrates and material interfaces/junctions, demonstrating that an Ohmic-contact superconducting-normal transmission line is optimal for a hybrid system with self-reflections at less than -25 dB over an operating range of 300 GHz. Finally, a unified layout and lithography construction process is proposed by which such a hybrid system could be developed in a monolithic physical system on a hybrid substrate while maintaining material and layout integrity under varying process temperatures.
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    SRAM design leveraging material properties of exploratory transistors
    (Elsevier, 2022) Gopinath, Anoop; Cochran, Zachary; Ytterdal, Trond; Rizkalla, Maher; Electrical and Computer Engineering, Purdue School of Engineering and Technology
    While MOSFET miniaturization continues to face increased challenges related to process variations, supply voltage scaling and leakage currents, exploratory devices such as Graphene Nanoribbon Field Effect Transistors (GNRFET), Tunnel Field Effect Transistor (TFET), and Carbon Nanotube Field Effects Transistors (CNFET) could provide solutions for continued device scaling with better power/performance trade-offs. The GaN TFET used in this work is a heterojunction device, where the material properties of Ga and N result in a bandgap of 3.2eV and ultra-low IOFF current. Moreover, the properties of Ga and N result in a steep-switching device with a subthreshold swing of 30mV/decade. The structure of graphene material results in high conductivity of electrons, even at very high operating temperatures, making GNRFETs a high-performance device. However, graphene specific line-edge roughness can degrade performance, and thus process related variations can have a negative impact for GNRFETs. In CNFETs, the mobility and the velocity of the conducting carriers are functions of the carbon nanotube and the gate length. The length and the diameter of the carbon nanotube material adds parasitic capacitance and resistance to the model, contributing to slower speed of the device. In this paper, the impact on power, performance, and static noise margins (SNM) of the traditional single-port 6T-SRAM and modified single-port 8T-SRAMs designed using exploratory devices are analyzed with a set figure of merit (FOM), elucidating the material properties of the devices. The results obtained from this work show that GNRFET-based SRAM have very high performance with a worst-case memory access time of 27.7 ps for a 16x4-bit 4-word array while CNFET-based SRAM bitcell consume the lowest average power during read/write simulations at 3.84 µW, while TFET- based SRAM bitcell show the best overall average and static power consumption at 4.79 µW and 57.8 pW. A comparison of these exploratory devices with FinFET and planar CMOS showed that FinFET-based SRAM bitcell consumed the lowest static power at 39.8 pW and CMOS-based SRAM had the best read, write, and hold SNMs of 201 mV, 438 mV and 413 mV respectively.