Browsing by Author "Balasubramanian, Linknath Surya"

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    ASIC implemented MicroBlaze-based Coprocessor for Data Stream Management Systems
    (2020-05) Balasubramanian, Linknath Surya; Lee, John J.; Christopher, Lauren A; Rizkalla, Maher E.
    The drastic increase in Internet usage demands the need for processing data in real time with higher efficiency than ever before. Symbiote Coprocessor Unit (SCU), developed by Dr. Pranav Vaidya, is a hardware accelerator which has potential of providing data processing speedup of up to 150x compared with traditional data stream processors. However, SCU implementation is very complex, fixed, and uses an outdated host interface, which limits future improvement. Mr. Tareq S. Alqaisi, an MSECE graduate from IUPUI worked on curbing these limitations. In his architecture, he used a Xilinx MicroBlaze microcontroller to reduce the complexity of SCU along with few other modifications. The objective of this study is to make SCU suitable for mass production while reducing its power consumption and delay. To accomplish this, the execution unit of SCU has been implemented in application specific integrated circuit and modules such as ACG/OCG, sequential comparator, and D-word multiplier/divider are integrated into the design. Furthermore, techniques such as operand isolation, buffer insertion, cell swapping, and cell resizing are also integrated into the system. As a result, the new design attains 67.9435 µW of dynamic power as compared to 74.0012 µW before power optimization along with a small increase in static power, 39.47 ns of clock period as opposed to 52.26 ns before time optimization.
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    Microblaze-Based Coprocessor for Data Stream Management System
    (2019) Alqaisi, Tareq S.; Balasubramanian, Linknath Surya; Yadav, Avinash; Lee, John J.; Electrical and Computer Engineering, School of Engineering and Technology
    Data generation speed and volume have increased exponentially with the boom in Internet usage and with the advent of Internet of Things (IoT). Consequently, the need for processing these data faster and with higher efficiency has also grown in-over time. Many previous works tried to address this need and among them is Symbiote Coprocessor Unit (SCU), an accelerator capable of providing speedup of up to 150x compared with traditional data stream processors. The proposed architecture aims to reduce the complexity of SCU, making it flexible and still retaining its performance. The new design is more software driven and thus is very easy to be altered in the future if needed. We have also changed the older interface to industrial standard PCIe interface and AMBA AXI4 bus interconnect in order to make the design simple and open for future expansions.
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    Towards No-Penalty Control Hazard Handling in RISC Architecture Microcontrollers
    (2024-08) Balasubramanian, Linknath Surya; Rizkalla, Maher E.; Lee, John J.; Ytterdal, Trond; Kumar, Mukesh
    Achieving higher throughput is one of the most important requirements of a modern microcontroller. It is therefore not affordable for it to waste a considerable number of clock cycles in branch mispredictions. This paper proposes a hardware mechanism that makes microcontrollers forgo branch predictors, thereby removing branch mispredictions. The scope of this work is limited to low cost microcontroller cores that are applied in embedded systems. The proposed technique is implemented as five different modules which work together to forward required operands, resolve branches without prediction, and calculate the next instruction's address in the first stage of an in-order five stage pipelined micro-architecture. Since the address of successive instruction to a control transfer instruction is calculated in the first stage of pipeline, branch prediction is no longer necessary, thereby eliminating the clock cycle penalties occurred when using a branch predictor. The designed architecture was able to successfully calculate the address of next correct instruction and fetch it without any wastage of clock cycles except in cases where control transfer instructions are in true dependence with their immediate previous instructions. Further, we synthesized the proposed design with 7nm FinFET process and compared its latency with other designs to make sure that the microcontroller's operating frequency is not degraded by using this design. The critical path latency of instruction fetch stage integrated with the proposed architecture is 307 ps excluding the instruction cache access time.