Browsing by Author "Alqaisi, Tareq S."

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    Microblaze-Based Coprocessor for Data Stream Management System
    (2019) Alqaisi, Tareq S.; Balasubramanian, Linknath Surya; Yadav, Avinash; Lee, John J.; Electrical and Computer Engineering, School of Engineering and Technology
    Data generation speed and volume have increased exponentially with the boom in Internet usage and with the advent of Internet of Things (IoT). Consequently, the need for processing these data faster and with higher efficiency has also grown in-over time. Many previous works tried to address this need and among them is Symbiote Coprocessor Unit (SCU), an accelerator capable of providing speedup of up to 150x compared with traditional data stream processors. The proposed architecture aims to reduce the complexity of SCU, making it flexible and still retaining its performance. The new design is more software driven and thus is very easy to be altered in the future if needed. We have also changed the older interface to industrial standard PCIe interface and AMBA AXI4 bus interconnect in order to make the design simple and open for future expansions.
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    Microblaze-based coprocessor for data stream management systems
    (2017-12-06) Alqaisi, Tareq S.; Lee, John
    Data network's speed and availability are increasing at a record rate. More and more devices are now able to connect to the Internet and stream data. Processing this ever-growing amount of data in real time continues to be a challenge. Multiple studies have been conducted to address the growing demands for real-time processing and analysis of continuous data streams. Developed in a previous work, Symbiote Coprocessor Unit (SCU) is a hardware accelerator capable of providing up to 150X speedup over traditional data stream processors in the field of data stream management systems. However, SCU implementation is very complex, fixed, and uses an outdated host interface, which limits future improvements. In this study, we present a new SCU architecture that is based on a Xilinx MicroBlaze configurable microcontroller. The proposed architecture reduces complexity, allows future implementations of new algorithms in a relatively short amount of time while maintaining the SCU's high performance. It also has an industry standard PCIe interface. Finally, it uses a standard AMBA AXI4 bus interconnect, which enables easier integration of new hardware components. The new architecture is implemented using a Xilinx VC709 development board. Our experimental results have shown a minimal loss of performance as compared to the original SCU while providing a flexible and simple design.