Lee, Jaehwan JohnBarnes, Christopher J.King, Brian S.Chien, Yung Ping Stanley2010-07-272010-07-272010https://hdl.handle.net/1805/2222http://dx.doi.org/10.7912/C2/2574Indiana University-Purdue University Indianapolis (IUPUI)Industry trends indicate that many-core heterogeneous processors will be the next-generation answer to Moore's law and reduced power consumption. Thus, both academia and industry are focused on the challenges presented by many-core heterogeneous processor designs. In many cases, researchers use discrete event simulators to research and validate new computer architecture innovations. However, there is a lack of dynamically configurable discrete event simulation environments for the testing and development of many-core heterogeneous processors. To fulfill this need we present Mhetero, a retargetable framework for cycle-accurate simulation of heterogeneous many-core processors along with the cycle-accurate simulation of their associated network-on-chip communication infrastructure. Mhetero is the result of research into dynamically configurable and highly flexible simulation tools with which users are free to produce custom instruction sets and communication methods in a highly modular design environment. In this thesis we will discuss our approach to dynamically configurable discrete event simulation and present several experiments performed using the framework to exemplify how Mhetero, and similarly constructed simulators, may be used for future innovations.en-USMany-core heterogeneous processorsProcessor Simulator MheteroComputer architectureComputer simulation